1. Field of the Invention
This invention generally relates to static random access memory (SRAM) devices; and more specifically, the invention relates to a back gate controlled SRAM device.
2. Background Art
An SRAM is a semiconductor device that allows data to be stored in a static manner—that is, in a manner that does not require any refresh cycles to maintain the stored data—and SRAMs are now a key component in microelectronic chips/applications. As the dimension of semiconductor technology scales down, the process variations including random doping fluctuation would be the crucial factor of the SRAM design. When large process variation for aggressively scaled device dimension occurs, threshold voltages of two neighbor transistors in a conventional 6-transistor (6T) SRAM cell, as shown in FIG. 1, can be significantly different and the stability of SRAM cell deteriorates. The stability of a SRAM cell is often quantified by the static noise margin (SNM). The reduction of SNM threatens reliable functionality of SRAM, and, as a result, it may hinder the scaling of SRAM cell size in the future semiconductor technology to ensure the correct memory function. While the use of a large SRAM cell gives higher stability so that it is possible to maintain correct memory read and write functionalities, the area penalty due to the large SRAM cell size is intolerable. Since SRAM cell arrays consume most of the area in the modern microprocessor chip, design of a small SRAM cell is crucial for the design of very large scale integration (VLSI) systems.
One way to increase stability of SRAM is the use of 10-transistor (10T) SRAM cell, as illustrated in FIG. 2, instead of the conventional 6-transistor (6T) SRAM cell, shown in FIG. 1. In 10T SRAM cell, the cell node voltages are decoupled from the bit lines in READ mode so that the cell node voltages are not disturbed by the READ current. Hence, degradation of SNM in READ mode does not occur while the SNM in READ mode of conventional 6T SRAM is worse than SNM in STAND-BY mode. The 10T SRAM cell design approach also has large area consumption problem due to the increased number of transistors in a cell (from 6 to 10) although it is scalable to future technologies.
8-Transistor (8T) SRAM cell, as shown in FIG. 3, is an alternative to 10T SRAM cell. 2 transistors from 10T SRAM cell are removed in 8T SRAM cell by cutting down one of the differential bit lines. As the result, the 8T SRAM cell has the single-ended READ path while 10T SRAM cell has differential bit lines for READ operations. Although the 8T SRAM cell has the smaller area than the 10T SRAM cell has, single-end sensing scheme requires the higher bit line voltage development for correct sensing and it may limit the number of cells per sense amplifier. Hence, the area of 8T SRAM array may not be smaller than 10T SRAM array in system perspective.